The present invention relates to a clock generating circuit and a clock generating method thereof, and more particularly, to a clock generating circuit for dividing a clock to generate multi-phase clocks, and a clock generating method thereof.
Recently, semiconductor devices have begun to use multi-phase clocks in order to obtain high-speed operation. For example, a semiconductor device may use four reference clocks having 90-degree phase difference to generate four pulses having pulse widths corresponding to the phase difference of each clock. In this way, the semiconductor device can perform high-speed operation at four times the frequency of the reference clock. A phase locked loop circuit has been used to generate multi-phase clocks.
FIG. 1 illustrates a typical phase locked loop circuit that generates multi-phase clocks.
Referring to FIG. 1, the phase locked loop circuit includes a phase detector 101, a charge pump 103, a loop filter 105, a voltage controlled oscillator 107, and a divider 109.
The phase detector 101 compares a phase of a reference clock CLK with a phase of a divided clock CLK_DIV outputted from the divider 109. The phase detector 101 outputs an up signal UP when the phase of the reference clock CLK leads the phase of the divided clock CLK_DIV, and outputs a down signal DN when the phase of the reference clock CLK lags behind the phase of the divided clock CLK_DIV.
The charge pump 103 converts the up signal UP and the down signal DN into a voltage signal and outputs the voltage signal to the loop filter 105.
The loop filter 105 filters high-frequency components from the output signal of the charge pump 103 and outputs a control voltage VCTRL.
The voltage controlled oscillator 107 includes a ring-oscillator structure of delay cells 111, 113, 115 and 117. That is, the delay cells 111, 113, 115, and 117 are connected in cascade, and an output signal of the final delay cell 117 is inputted to the first delay cell 111. The output signals of the rest delay cells are inputted to their next delay cells, respectively. The delay amount of the delay cells 111, 113, 115 and 117 is controlled according to the control voltage VCTRL.
The number and phase difference of the multi-phase clocks are determined by the number and delay amount of the delay cells 111, 113, 115, and 117. For example, if the voltage controlled oscillator 107 is configured with two delay cells, four multi-phase clocks having 90-degree phase difference are generated. If the voltage controlled oscillator 107 is configured with four delay cells 111, 113, 115 and 117 as illustrated in FIG. 1, eight multi-phase clocks having 45-degree phase difference are generated.
The divider 109 divides the frequency of the multi-phase clocks CLKP1 to CLKP8, as represented by the clock signal CLKP4, to output the divided clock CLK_DIV. The divider 109 generates a low frequency clock by dividing the high frequency clock, a phase difference comparison of which is difficult, at a proper division ratio.
Since the phase locked loop circuit occupies a large area, the layout area of the semiconductor device including the phase locked loop circuit is increased, leading to an increase in power consumption. Furthermore, since the phase difference of the multi-phase clocks is determined by the delay amount of the delay cells, the phase difference of the multi-phase clocks will be varied if the delay amount of each delay cell is differently changed due to the influence of external noise or the like.